Modeling the Relationship between Fpga Architecture and Place and Route Runtime
نویسندگان
چکیده
This paper presents an analytical model that relates the architectural parameters of an FPGA to the place-and-route runtimes of the FPGA CAD tools. We consider both a simulated annealing based placement algorithm employing a bounding-box wirelength cost function, and a negotiationbased A* router. We also show an example application of the model in early architecture evaluation.
منابع مشابه
Place and Route Techniques for FPGA Architecture Advancement
Place and Route Techniques for FPGA Architecture Advancement
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